A bucket brigade circuit is a sequence of switching transistors interconnecting capacitive storage nodes, with the gates of alternate transistors in the sequence being driven by non-overlapping clock pulses. Bucket brigade circuits may be embodied advantageously in field effect transistor technology providing a bucket brigade cell which is simple in structure and manufacture. A voltage (charge) signal representative of the unit of binary information is introduced at the source of a first one of the FET bucket brigade cells. When the clock pulse on the gate of the first bucket brigade cell appears it bootstraps the previously restored drain node, causing current to flow through the FET device, and the unit of binary information is transferred to the storage capacitance between the first cell and the second cell. Thereafter, when the clock pulse on the gate of the second bucket brigade cell appears, the unit of binary information stored at the capacitive node between the first cell and the second cell is then transferred through the second cell to the restored capacitive node between the second cell and the third cell. In this manner, a voltage (charge) signal may be transferred through a string of bucket brigade cells using a two-phase clock to accomplish a serial storage, signal transfer, or signal processing operation. This operation is shown schematically in FIG. 1d. For each transfer there is always one cell which was initially empty of propagated charge. This empty cell is restored to a reference potential at the last device in a string and is essentially propagated in the reverse direction of information flow. Thus, for a two-phase clock, one needs 2 N cells to store N bits of information. The number of cells can be reduced to ##EQU1## for a multi (m) phase clock storing N bits of information.
A successful bucket brigade cell design must possess a number of attributes. Since bucket brigade cells are not used in isolation but are used in chain-like configurations, employing large numbers thereof, the cell must be of small dimension and be amenable to fabrication in high density integrated circuit arrangements. Since long chains of these cells are required for many applications, the transfer efficiency of each cell must be very close to unity and that transfer efficiency must not be different between that for the transfer of a binary zero signal and that for the transfer of a binary one signal.
A typical prior art implementation of a bucket brigade cell is shown in FIG. 1a with a cross-section of the cell along line 1b shown in FIG. 1b and a cross-section of the cell along the line 1c shown in FIG. 1c. The bucket brigade cell shown in FIGS. 1a-1c is of the metal gate type, which, although not having a self-aligned gate, utilizes a more simplified fabrication process than polycrystalline silicon self-aligned gate devices do, resulting in a more planar surface contour on which finer resolution photolithography can be performed. The prior art bucket brigade cell is formed as part of an integrated circuit in a P-type semiconductor substrate 2 and has an n+ type diffusion 4 which serves as its capacitive storage node. Under the thick oxide layer 6 in FIG. 1b, is the diffusion 4' whose right hand side serves as the source in the bucket brigade device 12 and whose left hand side serves as a portion of the drain for the bucket brigade device to the left of device 12. Generally, the prior art bucket brigade cell shown in FIG. 1b has a thick layer 6 of silicon dioxide which serves to separate the gates 12 and 14 of adjacent bucket brigade cells. Formed between the thick layers 6 of silicon dioxide is a thinner layer of silicon dioxide which consists of a relatively thinner portion 8 having a thickness typically on the order of 500 A to 1000 A and a relatively thicker portion 10 having a thickness generally on the order of 1000 A to 1500 A. The gate metal 12 of the bucket brigade cell is deposited and photolithographically delineated between the thick layers 6 of silicon dioxide over the thin oxide layers 8 and 10. Differential oxide thickness beneath the gate electrode 12 of a nonself-aligned gate FET device, in the region 3 between regions 6 and 8 of FIG. 1b, is desirable as taught in the prior art, to reduce parasitic capacitive coupling between the gate 12 and source 4' diffusion. Indeed, such devices are desired to be present on the LSI chip, which may also contain a bucket brigade chain, in order to perform other logical and input/output operations. The prior art process for forming the thicker region 3 relies on the enhanced oxidation rate of heavily doped silicon, such as the diffusion 4'. However, with this benefit comes the detriment of the growth of a corresponding thicker oxide layer 10 over the diffusion 4, which also reduces the capacitance between the gate 12 and the diffusion 4. The detrimental effect of this occurs when the FET device is employed as an element in a bucket brigade chain, since the charge storage node of the cell formed between the gate and diffusion will have a reduced capacitance per unit area.
The capacitive storage portion of the bucket brigade cell generally is located at the portion of the thin oxide layer 10 and the field effect switching portion of the bucket brigade cell is generally localized at the portion 8 of the thin oxide layer. This prior art bucket brigade cell suffers defects which are typical of the prior art. The prior art has not recognized nor solved the problem of including on the same IC chip both differential oxide FET logic devices and bucket brigade devices having a minimized thickness of the silicon dioxide layer 10 in the capacitive storage region, to maximize the capacitance per unit area thereof while at the same time maximizing the thickness of the oxide in region 3, in FIG. 1b, to minimize capacitive coupling to the source. Charge propagation along a bucket brigade chain as shown in FIG. 1d, is the result of a capacitive bootstrapping operation, where the magnitude of charge propagated from node-to-node is a function of the difference in magnitude between the gate-to-source capacitance C.sub.gs and the gate-to-drain capacitance C.sub.gd. The larger C.sub.gd is with respect to C.sub.gs, the larger will be the magnitude of the charge transferred. Since the minimum capacitance per bucket brigade cell is required to achieve a detectable output signal for a particular application, the cell must be made larger in area to meet the capacitance requirement.
Still other problems with the prior art bucket brigade cell, as is typified by that shown in FIG. 1a-1c, revolve about the inability to provide for self-alignment of the structural elements of the bucket brigade cell so that the spacing "X", which is required for alignment tolerance between the diffusion 4 and the gate oxide etching levels force the designer to make the separation distance "Y" wider between the diffusions 4a and 9 of devices in adjacent chains of bucket brigade cells. Still another set of problems associated with the prior art bucket brigade device cells concerns channel shortening effects which occur when adjacent cells within the same bucket brigade chain are brought too closely together. Because of the substantial vertical depth of the diffusion 4 in FIG. 1b as it faces the channel region between the diffusion 4 and the diffusion 4', as the separation distance between the diffusions 4 and 4' is reduced, the threshold voltage of the field effect transistor portion of the bucket brigade device beneath the thin oxide layer 8 becomes sensitive to the magnitude of the voltage difference between the diffusions 4 and 4'. This causes the threshold voltage, and therefore the charge transfer efficiency of the device to be different for binary one signals than it would be for binary zero signals. Since the threshold voltage and charge transfer efficiency has become dependent upon the logical value of the signal transferred, long chains of such bucket brigade cells will introduce a degradation in the signal transferred especially apparent in the first different bit in a sequence.